C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 221
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
17.2.1. Configuring Ports Which are Not Pinned Out
Although P4, P5, P6, and P7 are not brought out to pins on the C8051F041/3/5/7 devices, the Port Data
registers are still present and can be used by software. Because the digital input paths also remain active,
it is recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary power dissi-
pation arising from the inputs floating to non-valid logic levels. This condition can be prevented by any of
the following:
17.2.2. Configuring the Output Modes of the Port Pins
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull
configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to
GND, and a logic 1 will cause the Port pin to be driven to V
the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will
cause the Port pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent
contention between devices in systems where the Port pin participates in a shared interconnection in
which multiple outputs are connected to the same physical wire.
The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective
PnMDOUT Output Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding
port pin (see SFR Definition 17.17, SFR Definition 17.19, SFR Definition 17.21, and SFR Definition 17.23).
For example, to place Port pin 4.3 in push-pull mode (digital output), set P4MDOUT.3 to logic 1. All port
pins default to open-drain mode upon device reset.
17.2.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to "Open-Drain" in the PnMDOUT reg-
ister and writing a logic 1 to the associated bit in the Port Data register. For example, P7.7 is configured as
a digital input by setting P7MDOUT.7 to a logic 0, which selects open-drain output mode, and P3.7 to a
logic 1, which disables the low-side output driver.
17.2.4. Weak Pullups
By default, each Port pin has an internal weak pullup device enabled which provides a resistive connection
(about 100 k) between the pin and V
logic 1 to the Weak Pullup Disable bit, (WEAKPUD, XBR2.7). The weak pullup is automatically deactivated
on any pin that is driving a logic 0; that is, an output pin will not contend with its own pullup device.
17.2.5. External Memory Interface
If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE
(XBR2.5) should be set to a logic 0.
If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the
External Memory Interface will control the output states of the affected Port pins during the execution
phase of the MOVX instruction, regardless of the settings of the Port Data registers. The output configura-
tion of the Port pins is not affected by the EMIF operation, except that Read operations will explicitly dis-
able the output drivers on the Data Bus during the MOVX execution. See
Memory Interface and On-Chip XRAM” on page 187
Interface.
1. Leave the weak pullup devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.
2. Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing PnOUT = 0xFF.
3. Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data regis-
ters: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.
DD
. The weak pullup devices can be globally disabled by writing a
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
for more information about the External Memory
DD
. In the Open-Drain configuration, a logic 0 in
Section “16. External Data
221