C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 69
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
6.
The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multi-
plexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approxima-
tion-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram
in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable
under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used
by ADC0 is selected as described in
C8051F042/4/6 devices, or
C8051F043/5/7 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low
power shutdown when this bit is logic 0.
6.1.
The analog multiplexer can input analog signals to the ADC from four external analog input pins, Port 3
port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, and an internally
connected on-chip temperature sensor (temperature transfer function is shown in Figure 6.6). AMUX input
pairs can be programmed to operate in either differential or single-ended mode. This allows the user to
select the best measurement technique for each input channel, and even accommodates mode changes
"on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers associated
with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), the Configuration register
AMX0CF (SFR Definition 6.1), and the Port Pin Selection register AMX0PRT (SFR Definition 6.3).
Table 6.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-
ration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
AGND
10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
I/O Pins
Analog Multiplexer and PGA
Analog
Port 3
Input
Input
Pins
HV
SENSOR
TEMP
AMX0CF
ADC0GTH
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
AMUX
(SE or
9-to-1
DIFF)
AMX0SL
Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117
ADC0GTL
X
Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113
+
-
AV+
AD0EN
AGND
ADC0CF
ADC0LTH
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
ADC
10-Bit
AV+
SAR
ADC0CN
ADC0LTL
Start Conversion
10
20
10
Comb.
00
01
10
11
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD0WINT
for
for
69