C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 230
![IC 8051 MCU 64K FLASH 100TQFP](/photos/12/20/122007/c8051f040-gq_sml.jpg)
C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
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Quantity
Price
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Quantity:
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Company:
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Manufacturer:
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C8051F040-GQR
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Note 1: If Phase_Seg1 + Phase_Seg2 is even, then Phase_Seg2 = Phase_Seg1.
Note 2: Phase_Seg2 should be at least 2 t
C8051F040/1/2/3/4/5/6/7
We will adjust the length of the 4 bit segments so that their sum is as close as possible to the desired bit
time. Since each segment must be an integer multiple of the time quantum (t
time is 22 t
Prop_Seg must be greater than or equal to the propagation delay of 400 ns; we choose 9 t
The remaining time quanta (t
shown in Figure 18.1. We select Phase_Seg1 = 6 t
The Synchronization Jump Width (SJW) timing parameter is defined by Figure 18.2. It is used for determin-
ing the value written to the Bit Timing Register and for determining the required oscillator tolerance. Since
we are using a quartz crystal as the system clock source, an oscillator tolerance calculation is not needed.
The value written to the Bit Timing Register can be calculated using Equation 18.3. The BRP Extension
register is left at its reset value of 0x0000.
The following steps are performed to initialize the CAN timing registers:
230
BRPE = BRP - 1 = BRP Extension Register = 0x0000
SJWp = SJW - 1 = min ( 4, 6 ) – 1 = 3
TSEG1 = (Prop_Seg + Phase_Seg1 - 1) = 9 + 6 - 1 = 14
TSEG2 = (Phase_Seg2 - 1) = 5
Bit Timing Register = (TSEG2 * 0x1000) + (TSEG1 * 0x0100) + (SJWp * 0x0040) + BRPE = 0x5EC0
Step 1. Set the SFRPAGE register to CAN0_PAGE.
Step 2. Set the INIT the CCE bits to ‘1’ in the CAN Control Register accessible through the
Step 3. Set the CAN0ADR to 0x03 to point to the Bit Timing Register.
q
(994.642 ns), yielding a bit rate of 1.00539 Mbit/sec. The Sync_Seg is a constant 1 t
CAN0CN SFR.
Equation 18.3. Calculating the Bit Timing Register Value
Equation 18.2. Synchronization Jump Width (SJW)
Phase_Seg1
Equation 18.1. Assigning the Phase Segments
SJW = min ( 4, Phase_Seg1 )
q
) in the bit time are divided between Phase_Seg1 and Phase_Seg2 as
+
Phase_Seg2
q
.
=
Rev. 1.5
q
Bit Time
and Phase_Seg2 = 6 t
–
Sync_Seg
+
Prop_Seg
q
.
q
), the closest achievable bit
q
(406.899 ns).
q
. The
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