C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 37
![IC 8051 MCU 64K FLASH 100TQFP](/photos/12/20/122007/c8051f040-gq_sml.jpg)
C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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4.
MONEN
VREFA
VREF0
VREF2
AIN0.0
DGND
AGND
XTAL1
XTAL2
Name
VREF
VREF
/RST
TMS
TDO
TCK
V
AV+
TDI
Pinout and Package Definitions
DD
F040/2/4/6 F041/3/5/7
37, 64, 90
38, 63, 89
8, 11, 14
9, 10, 13
26
27
28
12
16
17
15
18
Pin Numbers
1
2
3
4
5
24, 41, 57
25, 40, 56
3, 6
4, 5
58
59
60
61
62
17
18
19
7
8
9
Table 4.1. Pin Definitions
D Out JTAG Test Data Output with internal pullup. Data is
A Out Crystal Output. This pin is the excitation driver for a crystal
Type Description
D I/O Device Reset. Open-drain output of internal V
A I/O Bandgap Voltage Reference Output (all devices).
D In
D In
D In
A In
D In
A In
A In
A In
A In
A In
Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
Analog Ground. Must be tied to Ground.
JTAG Test Mode Select with internal pullup.
JTAG Test Clock with internal pullup.
JTAG Test Data Input with internal pullup. TDI is latched
on the rising edge of TCK.
shifted out on TDO on the falling edge of TCK. TDO out-
put is a tri-state driver.
Is driven low when V
external source can initiate a system reset by driving this
pin low.
Crystal Input. This pin is the return for the internal oscilla-
tor circuit for a crystal or ceramic resonator. For a preci-
sion internal clock, connect a crystal or ceramic resonator
from XTAL1 to XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
or ceramic resonator.
V
internal V
V
disabled.
In most applications, MONEN should be connected
directly to V
DAC Voltage Reference Input (C8051F041/3 only).
ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only)
Voltage Reference Input.
ADC0 Voltage Reference Input.
ADC2 Voltage Reference Input (C8051F040/2 only).
DAC Voltage Reference Input (C8051F040/2 only).
ADC0 Input Channel 0 (See ADC0 Specification for com-
plete description).
Rev. 1.5
DD
DD
Monitor Enable. When tied high, this pin enables the
is < 2.7 V. When tied low, the internal V
C8051F040/1/2/3/4/5/6/7
DD
monitor, which forces a system reset when
DD
.
DD
is < 2.7 V and MONEN is high. An
DD
DD
monitor is
monitor.
37
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