C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 92
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F040/1/2/3/4/5/6/7
7.2.
ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a
divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock
divided by (AD2SC + 1) for 0 AD2SC 31). The maximum ADC2 conversion clock is 7.5 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start
of Conversion Mode bits (AD2CM2–0) in ADC2CN. Conversions may be initiated by the following:
An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in the
digital crossbar
CNVSTR2 will be the external convert start signal for ADC2. However, if only CNVSTR0 is enabled in the
digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may serve as the start of conversion for
both ADC0 and ADC2. This permits synchronous sampling of both ADC0 and ADC2.
During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The
falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Con-
verted data is available in the ADC2 data word, ADC2.
When a conversion is initiated by writing a ‘1’ to AD2BUSY, it is recommended to poll AD2INT to determine
when the conversion is complete. The recommended procedure is:
7.2.2. Tracking Modes
According to Table 7.2, each ADC2 conversion must be preceded by a minimum tracking time for the con-
verted result to be accurate. The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode.
In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When
the AD2TM bit is logic 1, ADC2 operates in low-power tracking mode. In this mode, each conversion is pre-
ceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 (or
CNVSTR0, See Section 7.2.1 above) signal is used to initiate conversions in low-power tracking mode,
ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see
Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or
sleep modes. Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently
changed, due to the settling time requirements described in
ments” on page
92
ADC2 Modes of Operation
•Writing a ‘1’ to the AD2BUSY bit of ADC2CN;
•A Timer 3 overflow (i.e., timed continuous conversions);
•A rising edge detected on the external ADC convert start signal, CNVSTR2 or CNVSTR0 (see
•A Timer 2 overflow (i.e., timed continuous conversions);
•Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with a
Step 1. Write a ‘0’ to AD2INT;
Step 2. Write a ‘1’ to AD2BUSY;
Step 3. Poll AD2INT for ‘1’;
Step 4. Process ADC2 data.
important note below);
single software command).
(Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page
94.
Rev. 1.5
Section “7.2.3. Settling Time Require-
204),