C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 170
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F040/1/2/3/4/5/6/7
170
Bit7:
Bit6:
Bit5:
Bit0:
Bit4:
Bit3:
Bit2:
Bit1:
Bit7
R
-
Reserved.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write:
Read:
C0RSEF: Comparator0 Reset Enable and Flag.
Write:
Read:
SWRSF: Software Reset Force and Flag.
Write:
Read:
WDTRSF: Watchdog Timer Reset Flag.
MCDRSF: Missing Clock Detector Flag.
Write:
detected.
Read:
PORSF: Power-On Reset Flag.
Write: If the
bit can be written to select or de-select the
0: De-select the
1: Select the
Important: At power-on, the V
tor enable pin (MONEN). The PORSF bit does not disable or enable the V
cuit. It simply selects the V
Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on
reset or a V
following the reset.
0: Source of last reset was not a power-on or V
1: Source of last reset was a power-on or V
Note: When this flag is read as '1', all other reset flags are indeterminate.
PINRSF: HW Pin Reset Flag.
Write:
Read:
CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF
R/W
Bit6
0: CNVSTR0 is not a reset source.
1: CNVSTR0 is a reset source (active low).
0: Source of prior reset was not CNVSTR0.
1: Source of prior reset was CNVSTR0.
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
1: Forces an internal reset. /RST pin is not effected.
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.
0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.
0: No effect.
1: Forces a Power-On Reset. /RST is driven low.
0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.
0: No effect.
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
DD
V
SFR Definition 13.2. RSTSRC: Reset Source
V
DD
DD
monitor reset. In either case, data memory should be considered indeterminate
V
monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this
R/W
Bit5
DD
monitor as a reset source.
monitor as a reset source.
DD
R/W
Bit4
DD
monitor as a reset source.
monitor is enabled/disabled using the external V
Rev. 1.5
Bit3
R
V
DD
DD
monitor reset.
DD
monitor as a reset source.
monitor reset.
R/W
Bit2
PORSF
Bit1
R
SFR Address:
PINRSF
SFR Page:
R/W
Bit0
DD
monitor cir-
0xEF
0
00000000
Reset Value
DD
moni-