ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 169

• Manufacturer Part Number: ATTINY48-MMU
• Description: MCU AVR 5K FLASH 12MHZ 28-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, I2S, SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28VQFN EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8008G–AVR–04/11
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure
mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See
Figure 17-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
17-6. This assures a fixed delay from the trigger event to the start of conversion. In this
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
12
3
Sample &
Hold
4
13
Figure
5
14
6
17-7.
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
Sample & Hold
12
4
ATtiny48/88
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
169