ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 62

• Manufacturer Part Number: ATTINY48-MMU
• Description: MCU AVR 5K FLASH 12MHZ 28-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, I2S, SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28VQFN EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.2
10.2.3
10.2.4
62
ATtiny48/88
Toggling the Pin
Break-Before-Make Switching
Switching Between Input and Output
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an immedi-
ate tri-state period lasting one system clock cycle is introduced as indicated in
example, if the system clock is 4 MHz and the DDRxn is written to make an output, the immedi-
ate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise
BBMx enable bits. For details on BBMx bits, see
When switching the DDRxn bit from output to input there is no immediate tri-state period
introduced.
Figure 10-3. Break Before Make, switching between input and output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
INSTRUCTIONS
SYSTEM CLK
PORTx
DDRx
R17
R16
Px0
Px1
0x01
tri-state
out DDRx, r16
intermediate tri-state cycle
0x02
tri-state
nop
0x02
0x01
0x55
“PORTCR – Port Control Register” on page
out DDRx, r17
intermediate tri-state cycle
tri-state
0x01
Figure
8008G–AVR–04/11
10-3. For
77.