ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 5
![MCU AVR 5K FLASH 12MHZ 28-QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATTINY48-MMU
Manufacturer Part Number
ATTINY48-MMU
Description
MCU AVR 5K FLASH 12MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MMU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28VQFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2. Overview
2.1
8008G–AVR–04/11
Block Diagram
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
Block Diagram
8bit T/C 0
PORT D (8)
Analog
Comp.
PD[0:7]
Generation
Oscillator
Circuits /
EEPROM
Watchdog
Watchdog
Oscillator
Clock
Timer
16bit T/C 1
PORT B (8)
PB[0:7]
SPI
POR / BOD &
Supervision
Power
RESET
Flash
PORT C (8)
PC[0:7]
A/D Conv.
TWI
Bandgap
Internal
CPU
debugWIRE
6
PA[0:3] (in TQFP and MLF)
Program
SRAM
Logic
PORT A (4)
2
ATtiny48/88
RESET
CLKI
5
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