ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 108

• Manufacturer Part Number: ATMEGA8A-MUR
• Description: MCU AVR 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.2
17.3
17.4
8159D–AVR–02/11
Timer/Counter Clock Sources
Counter Unit
Definitions
Compare Unit” on page
which can be used to generate an Output Compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2
counter value and so on).
The definitions in
Table 17-1.
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
chronous Operation of the Timer/Counter” on page
prescaler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
17-2
Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surrounding environment.
count
direction
clear
DATA BUS
TCNTn
Definitions
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2 Register. The assignment is dependent
on the mode of operation.
Table 17-1
109. The Compare Match event will also set the Compare Flag (OCF2)
direction
count
are also used extensively throughout the document.
BOTTOM
clear
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Control Logic
T2
is by default equal to the MCU clock, clk
TOP
TOVn
(Int. Req.)
clk
Tn
Prescaler
118. For details on clock sources and
Oscillator
75.
T/C
ATmega8A
I/O
clk
. When the AS2
I/O
TOSC2
TOSC1
“Asyn-
Figure
108