ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 219
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ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.8.3
23.8.4
23.8.5
23.8.6
23.8.7
8159D–AVR–02/11
Performing a Page Write
Using the SPM Interrupt
Consideration While Updating BLS
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
Note:
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling
the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be
moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either page erase or page write), the RWW section is always blocked
for reading. The user software itself must prevent that this section is addressed during the self
programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is
busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as
described in
RWW section after the programming is completed, the user software must clear the RWWSB by
writing the RWWSRE. See
an example.
To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are
the Boot Lock Bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
See
Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the Lock Bits). For future compatibility
Bit
R0
• Page Write to the RWW section: The NRWW section can be read during the page write.
• Page Write to the NRWW section: The CPU is halted during the operation.
Table 23-2
If an interrupt occurs in the timed seqence the four cycle access cannot be guaranteed. In order to
ensure atomic operation disable interrupts before writing to SPMCSR.
“Interrupts” on page
and
7
1
Table 23-3
6
1
“Simple Assembly Code Example for a Boot Loader” on page 221
for how the different settings of the Boot Loader Bits affect the
BLB12
45, or the interrupts must be disabled. Before addressing the
5
BLB11
4
BLB02
3
BLB01
2
“Interrupts” on page
1
1
ATmega8A
0
1
45.
219
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