ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 110
ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.5.1
17.5.2
8159D–AVR–02/11
Force Output Compare
Compare Match Blocking by TCNT2 Write
Figure 17-3. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled
the CPU will access the OCR2 directly.
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the
OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match
had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
BOTTOM
FOCn
TOP
OCRn
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
OCFn (Int. Req.)
ATmega8A
OCxy
110
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