ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 193
ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.8.3
20.8.4
8159D–AVR–02/11
TWI Status Register – TWSR
TWDR – TWI Data Register
• Bits 7:3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from TWSR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-
caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 20-10. TWI Bit Rate Prescaler
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the Two-wire Serial Bus.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TWPS1
0
0
1
1
TWS7
TWD7
R/W
R
7
1
7
1
TWD6
TWS6
R/W
R
6
1
6
1
TWPS0
“Bit Rate Generator Unit” on page
0
1
0
1
TWD5
TWS5
R/W
R
5
1
5
1
TWS4
TWD4
R/W
R
4
1
4
1
TWS3
TWD3
Prescaler Value
1
4
16
64
R/W
R
3
1
3
1
TWD2
166. The value of TWPS1:0 is used
R/W
R
2
–
0
2
1
TWPS1
TWD1
R/W
R/W
1
0
1
1
ATmega8A
TWPS0
TWD0
R/W
R/W
0
0
0
1
TWDR
TWSR
193
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