ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 190
ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.7
8159D–AVR–02/11
Multi-master Systems and Arbitration
Figure 20-17. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
Figure 20-18. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
This is summarized in
• Two or more masters are performing identical communication with the same Slave. In this
• Two or more masters are accessing the same Slave with different data or direction bit. In this
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
case, neither the Slave nor any of the masters will know about the bus contention.
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
S
S = START
SDA
SCL
Transmitted from master to slave
SLA+W
TRANSMITTER
Device 1
Figure
MASTER
A
Master Transmitter
20-19. Possible status values are given in circles.
ADDRESS
TRANSMITTER
Device 2
MASTER
Device 3
A
RECEIVER
SLAVE
Rs = REPEATED START
Rs
Transmitted from slave to master
........
SLA+R
Device n
V
CC
A
R1
Master Receiver
DATA
ATmega8A
R2
P = STOP
A
P
190
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