ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 249
ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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25.7
8159D–AVR–02/11
2. Required only for f
3. C
4. f
5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f
SPI Timing Characteristics
Serial Bus need only obey the general f
6MHz for the low time requirement to be strictly met at f
will not be strictly met for f
at full speed (400kHz) with other ATmega8A devices, as well as any other device with a proper t
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
Figure 25-3. Two-wire Serial Bus Timing
See
Table 25-5.
SCL
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
SCL
SDA
Figure 25-4
> 100kHz.
SCL
t
SU;STA
> 308kHz when f
SS high to tri-state
SCK to out high
SCK to SS high
SCK high/low
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
SPI Timing Parameters
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
and
Setup
Setup
Hold
Hold
SCL
Figure 25-5
requirement.
(1)
t
CK
HD;STA
= 8MHz. Still, ATmega8A devices connected to the bus may communicate
t
of
t
LOW
for details.
SCL
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
= 100kHz.
t
HIGH
t
HD;DAT
t
LOW
4 • t
2 • t
2 • t
Min
10
10
20
ck
ck
ck
t
SU;DAT
SCL
SCL
See
50% duty cycle
- 2/f
- 2/f
0.5 • t
CK
CK
Table 18-4
Typ
3.6
), thus the low time requirement
10
10
10
10
15
15
10
), thus f
SCK
LOW
CK
acceptance margin.
t
ATmega8A
SU;STO
must be greater than
t
r
Max
1.6
t
BUF
ns
249
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