ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 191
ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.8
20.8.1
20.8.2
8159D–AVR–02/11
Register Description
TWBR – TWI Bit Rate Register
TWCR – TWI Control Register
Figure 20-19. Possible Status Codes Caused by Arbitration
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 166
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
START
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
Address / General Call
received
Direction
TWBR6
TWEA
Own
R/W
R/W
6
0
6
0
Yes
Arbitration lost in SLA
SLA
Write
Read
TWBR5
TWSTA
R/W
R/W
No
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
68/78
38
B0
Arbitration lost in Data
TWBR3
TWWC
R/W
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
R
3
0
3
0
Data
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
ATmega8A
“Bit Rate Generator
TWBR0
TWIE
R/W
R/W
0
0
0
0
STOP
TWBR
TWCR
191
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