AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 109

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.6
The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base
address.
Table 9-1.
Note:
The following addresses are used by SAU channel registers. All offsets are relative to the SAU’s HSB base address. The
number of channels implemented is device specific, refer to the Module Configuration section at the end of this chapter.
Table 9-2.
32099F–11/2010
0x04*n
Offset
Offset
0x0C
0x1C
0xFC
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x00
0x04
0x08
...
User Interface
1.
The reset values are device specific. Please refer to the Module Configuration section at the
SAU Configuration Register Memory Map
SAU Channel Register Memory Map
Channel Enable Register High
Channel Enable Register Low
Interrupt Disable Register
Remap Target Register 0
Remap Target Register 1
Remap Target Register 2
Remap Target Register n
Interrupt Enable Register
Interrupt Mask Register
Interrupt Clear Register
Configuration Register
Parameter Register
Control Register
Version Register
Unlock Register
Status Register
Register
Register
...
Register Name
Register Name
PARAMETER
VERSION
CONFIG
CERH
RTR0
RTR1
RTR2
RTRn
CERL
IMR
IER
IDR
ICR
UR
CR
SR
...
AT32UC3L016/32/64
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Read-only
Access
Access
...
end of this chapter.
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
Reset
N/A
N/A
N/A
N/A
N/A
-
-
...
(1)
(1)
109