AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 512
![MCU AVR32 64KB FLASH 48TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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- Download datasheet (13Mb)
22.8.8
32099F–11/2010
Identifying Bus Events
This chapter lists the different bus events, and how these affects bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
Table 22-5.
Event
Slave transmitter has sent a
data byte
Slave receiver has received
a data byte
Start+Sadr on bus, but
address is to another slave
Start+Sadr on bus, current
slave is addressed, but
address match enable bit in
CR is not set
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set,
SR.STREN and SR.SOAM
are set.
Repeated Start received
after being addressed
Stop received after being
addressed
Start, Repeated Start or
Stop received in illegal
position on bus
Data is to be received in
slave receiver mode,
SR.STREN is set, and RHR
is full
Data is to be transmitted in
slave receiver mode,
SR.STREN is set, and THR
is empty
Data is to be received in
slave receiver mode,
SR.STREN is cleared, and
RHR is full
Bus Events
Effect
SR.THR is cleared.
SR.BTF is set.
The value of the ACK bit sent immediately after the data byte is given
by CR.ACK.
SR.RHR is set.
SR.BTF is set.
SR.NAK updated according to value of ACK bit received from master.
None.
None.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction.
Slave enters appropriate transfer direction mode and data transfer
can commence.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction.
Slave stretches TWCK immediately after transmitting the address
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared.
Slave the enters appropriate transfer direction mode and data transfer
can commence.
SR.REP set.
SR.TCOMP unchanged.
SR.STO set.
SR.TCOMP set.
SR.BUSERR set.
TWCK is stretched until RHR has been read.
TWCK is stretched until THR has been written.
TWCK is not stretched, read data is discarded.
SR.ORUN is set.
AT32UC3L016/32/64
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