AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 511
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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22.8.6.2
22.8.6.3
22.8.7
32099F–11/2010
Wakeup from Sleep Modes by TWI Address Match
Timeouts
SMBALERT
and the slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC
error occurred.
In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after
all data bytes have been transmitted. Upon reception of this PEC byte, the master will com-
pare it to the PEC value it has computed itself. If the values match, the data was received
correctly. If the PEC values differ, data was corrupted, and the master must take appropriate
action.
The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled
when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if
PEC enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number
of data bytes in the transmission, including the PEC byte.
The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave
will leave the bus. The SR.SMBTOUT bit is also set.
A slave can get the master’s attention by pulling the SMBALERT line low. This is done by set-
ting the CR.SMBAL bit. This will also enable address match on the Alert Response Address
(ARA).
The TWIS is able to wake the device up from sleep modes upon an address match, including
modes where CLK_TWIS is stopped. If a TWI Start condition is received in a sleep mode
where CLK_TWIS is stopped, TWIS will stretch TWCK until CLK_TWIS has started. The time
required for restarting CLK_TWIS depends on which sleep mode the system was in.
When CLK_TWIS has been restarted, the TWCK stretching is released and the slave address
will be received on the TWI bus. To save power, only a limited part of the device including
TWIS receives a clock at this time. If the address phase causes a TWIS address match, the
entire device will be wakened and normal TWIS address match actions performed. Normal
TWI transfer will then follow. If the TWIS was not addressed by the transfer, CLK_TWIS will
automatically be stopped and the system will go back to the original sleep mode.
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