AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 507
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 507 of 858
- Download datasheet (13Mb)
22.8.2.4
22.8.2.5
22.8.3
32099F–11/2010
Slave Transmitter Mode
Clock Stretching
Bus Errors
Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.
TWIS may extend the TWCK low period after each byte transfer if CR.STREN=1 and:
If CR.STREN=0 and:
If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set
and TWIS waits for a new START condition.
If TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it
will enter slave transmitter mode and set the SR.TRA bit.
After the address phase, the following actions are performed:
• The address in CR.ADR is checked for address match if CR.SMATCH is set.
• The Alert Response Address is checked for address match if CR.SMAL is set.
• The Default Address is checked for address match if CR.SMDA is set.
• The Host Header Address is checked for address match if CR.SMHH is set.
• Module is in slave transmitter mode, data should be transmitted, but THR is empty, or
• Module is in slave receiver mode, a byte has been received and placed into the internal
• Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains
• Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit
• Module is in slave receiver mode, a byte has been received and placed into the internal
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes
2. Byte to transmit depends on I²C/SMBus mode and CR.PEC:
3. The data byte in the shifter is transmitted.
4. NBYTES is updated. If CR.CUP is set, NBYTES is incremented, otherwise NBYTES
5. After each data byte has been transmitted, the master transmits an ACK (Acknowl-
shifter, but RHR is full, or
stretched until all address match bits in SR have been cleared.
the value present in THR (the last transmitted byte or reset value), and set SR.URUN.
shifter, but RHR is full: Discard the received byte and set SR.ORUN.
to transmit. This is necessary in order to know when to transmit PEC byte. NBYTES
can also be used to count the number of bytes received if using DMA.
– If in I²C mode or CR.PEC=0 or NBYTES!=0: TWIS waits until THR contains a valid
– SMBus mode and CR.PEC=1: If NBYTES=0, the generated PEC byte is
is decremented.
edge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the
SR.NAK bit is changed to one, then the SR.BTF (Byte Transfer Finished) bit is
changed to one. The NAK indicates that the transfer is finished, and TWIS will wait for
a STOP or REPEATED START. If an ACK bit is received, the SR.NAK bit remains at
data byte, possibly stretching the low period of TWCK. After THR contains a valid
data byte, the data byte is transferred to a shifter, and then SR.TXRDY is changed
to one because the THR is empty again.
automatically transmitted instead of a data byte from THR. TWCK will not be
stretched by TWIS.
AT32UC3L016/32/64
507
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