AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 555
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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24.5.2
24.5.3
24.5.4
24.5.5
24.5.6
24.6
24.6.1
24.6.1.1
24.6.1.2
32099F–11/2010
Functional Description
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
TC Description
Channel I/O Signals
16-bit counter
When using the TIOA lines as inputs the user must make sure that no peripheral events are gen-
erated on the line. Refer to the Peripheral Event System chapter for details.
If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.
The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.
The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.
The TC peripheral events are connected via the Peripheral Event System. Refer to the Periph-
eral Event System chapter for details.
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.
The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in
As described in
Table 24-2.
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Sta-
tus Register (SRn.COVFS) is set.
Block/Channel
Channel Signal
Channel I/O Signals Description
Figure 24-1 on page
XC0, XC1, XC2
Signal Name
SYNC
TIOA
TIOB
INT
554, each Channel has the following I/O signals.
Figure 24-3 on page
Description
External Clock Inputs
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Output
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Input/Output
Interrupt Signal Output
Synchronization Input Signal
AT32UC3L016/32/64
570.
555
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