AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 477
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Figure 21-11. Arbitration Cases
21.8.7
21.8.7.1
32099F–11/2010
Data from a Master
TWI DATA transfer
Data from TWI
(DADR + W + START + Write THR)
Combined Transfers
ARBLST
A transfer is programmed
TWCK
Write Followed by Write
TWD
TWCK
TWD
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Programming NCMDR with START=1 when the previous transfer was programmed with
STOP=0 will cause a REPEATED START on the bus. The ability to generate such connected
transfers allows arbitrary transfer lengths, since it is legal to program CMDR with both
START=0 and STOP=0. If this is done in master receiver mode, the CMDR.ACKLAST bit must
also be controlled.
As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when
data to transmit can be written to the THR, or when received data can be read from RHR.
Transfer of data to THR and from RHR can also be done automatically by DMA, see
the Peripheral DMA Controller” on page 475
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
To generate this transfer:
1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
S
S
S
1
1
1
Transfer is stopped
0 0
0
0 0
1
1 1
1 1
TWI stops sending data
Arbitration is lost
(DADR + W + START + Write THR)
Transfer is programmed again
Data from the master
Bus is busy
Transfer is kept
P
P
Bus is free
Bus is considered as free
Transfer is initiated
S
S
S
AT32UC3L016/32/64
1
1
1
0
0 0
0
1
0
1 1
The master stops sending data
1 1
Arbitration is lost
Data from the TWI
”Using
477
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