AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 42
![MCU AVR32 64KB FLASH 48TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 42 of 858
- Download datasheet (13Mb)
7.3
7.4
7.4.1
7.4.2
7.4.3
32099F–11/2010
Block Diagram
Product Dependencies
Power Management
Clocks
Interrupts
Figure 7-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. It
is recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA
interrupts requires the interrupt controller to be programmed first.
High Speed
Bus Matrix
Controller
Interrupt
Memory
HSB
PDCA Block Diagram
HSB
HSB
IRQ
Peripheral DMA
HSB to PB
Controller
(PDCA)
Bridge
AT32UC3L016/32/64
Handshake Interfaces
Peripheral
Peripheral
Peripheral
Peripheral
(n-1)
0
1
2
42
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