AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 77
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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8. Flash Controller (FLASHCDW)
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
32099F–11/2010
Features
Overview
Product Dependencies
Power Management
Clocks
Interrupts
Rev: 1.0.2.0
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The Flash Controller (FLASHCDW) interfaces the on-chip flash memory with the 32-bit internal
HSB bus. The controller manages the reading, writing, erasing, locking, and unlocking
sequences.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the FLASHCDW, the FLASHCDW
will stop functioning and resume operation after the system wakes up from sleep mode.
T h e F L A S H C D W h a s t w o b u s c l o c k s c o n n e c t e d : O n e H i g h S p e e d B u s c l o c k
(CLK_FLASHCDW_HSB) and one Peripheral Bus clock (CLK_FLASHCDW_PB). These clocks
are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by
writing to the Power Manager. The user has to ensure that CLK_FLASHCDW_HSB is not turned
off before reading the flash or writing the pagebuffer and that CLK_FLASHCDW_PB is not
turned off before accessing the FLASHCDW configuration and control registers. Failing to do so
may deadlock the bus.
The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the
FLASHCDW interrupts requires the interrupt controller to be programmed first.
Controls on-chip flash memory
Supports 0 and 1 wait state bus access
Buffers reducing penalty of wait state in sequential code or loops
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle for sequential reads
Secure State for supporting FlashVault
32-bit HSB interface for reads from flash and writes to page buffer
32-bit PB interface for issuing commands to and configuration of the controller
Flash memory is divided into 16 regions can be individually protected or unprotected
Additional protection of the Boot Loader pages
Supports reads and writes of general-purpose Non Volatile Memory (NVM) bits
Supports reads and writes of additional NVM pages
Supports device protection through a security bit
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit
™
technology
AT32UC3L016/32/64
77
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