AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 480
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Figure 21-15. A Read Transfer with 10-bit Addressing
21.8.9
21.8.9.1
32099F–11/2010
S
1
SLAVE ADDRESS
1
SMBus Mode
1
1st 7 bits
Packet Error Checking
1
0
X
X
RW A1
0
SMBus mode is enabled and disabled by the SMEN and SMDIS bits in CR. SMBus mode
operation is similar to I²C operation with the following exceptions:
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing
CMDR.PECEN to one enables automatic PEC handling in the current transfer. Transfers with
and without PEC can freely be intermixed in the same system, since some slaves may not
support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that
PEC handling on combined transfers will be correct.
In master transmitter mode, the master calculates a PEC value and transmits it to the slave
after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will com-
pare it to the PEC value it has computed itself. If the values match, the data was received
correctly, and the slave will return an ACK to the master. If the PEC values differ, data was
corrupted, and the slave will return a NACK value. The DNAK bit in SR reflects the state of the
last received ACK/NACK value. Some slaves may not be able to check the received PEC in
time to return a NACK if an error occurred. In this case, the slave should always return an ACK
after the PEC byte, and some other mechanism must be implemented to verify that the trans-
mission was received correctly.
In master receiver mode, the slave calculates a PEC value and transmits it to the master after
all data bytes have been transmitted. Upon reception of this PEC byte, the master will com-
pare it to the PEC value it has computed itself. If the values match, the data was received
correctly. If the PEC values differ, data was corrupted, and the PECERR bit in SR is set. In
master receiver mode, the PEC byte is always followed by a NACK transmitted by the master,
since it is the last byte in the transfer.
The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled
when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if
PEC is enabled when NBYTES reaches zero. NBYTES must therefore be set to the total num-
ber of data bytes in the transmission, including the PEC byte.
1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,
2. Program NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
on the bus. These timeout values must be programmed into SMBTR.
Address (ARA) and Host Header (HH) Address.
NBYTES=0 and the desired address.
the desired address and NBYTES value.
SLAVE ADDRESS
2nd byte
A2
Sr
1
SLAVE ADDRESS
1
1
1st 7 bits
1
0
X
X
AT32UC3L016/32/64
RW A3
1
DATA
A
DATA
A
P
480
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