AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 472
![MCU AVR32 64KB FLASH 48TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 472 of 858
- Download datasheet (13Mb)
21.8.2.1
21.8.2.2
32099F–11/2010
Clock Generation
Setting up and Performing a Transfer
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the
TWCK clock. CWGR must be programmed so that the desired TWI bus timings are generated.
CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescal-
ing can be selected through the EXP field in CWGR.
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T
HIGH: Prescaled clock cycles in clock high count. Used to time T
STASTO: Prescaled clock cycles in clock high count. Used to time T
DATA: Prescaled clock cycles for data setup and hold count. Used to time T
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T
Any slave or other bus master taking part in the transfer may extend the TWCK low period at
any time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock
low time and the clock high time, but the TWCK rise and fall times are determined by the exter-
nal circuitry (capacitive load, etc.).
Figure 21-5. Bus Timing Diagram
Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). The following list presents the main steps in a typical communication:
f
prescaled
S
=
t
t LOW
HD:STA
-------------------------
2
(
EXP
f
clkpb
+ )
1
t
SU:DAT
)
t HIGH
t
HD:DAT
t LOW
t
t
SU:DAT
SU:STA
AT32UC3L016/32/64
HD_DAT
Sr
LOW
HIGH
+ T
. and T
HD_STA
.
SU_DAT
BUF
, T
t
HD_DAT
+ T
SU:STO
SU_STA
.
LOW
, T
.
, T
SU_DAT
P
SU_STO
472
.
.
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