ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 208

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.3
8284A–AVR–10/10
SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI Slave:
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO is configured as output and USCK pin is configured as input in the DDR Register. The
value stored in register r16 prior to the function is called is transferred to the master device, and
when the transfer is completed the data received from the Master is stored back into the r16
Register.
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop
is repeated until the USI Counter Overflow Flag is set.
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
init:
...
SlaveSPITransfer:
SlaveSPITransfer_loop:
ldi
sts
sts
ldi
sts
lds
sbrs
rjmp
lds
ret
r16,(1<<USIWM0)|(1<<USICS1)
USICR,r16
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16, USISR
r16, USIOIF
SlaveSPITransfer_loop
r16,USIDR
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