ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 226

IC MCU AVR 64K FLASH 64TQFP

ATMEGA649A-AU

Manufacturer Part Number
ATMEGA649A-AU
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA649A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA649A-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA649A-AUR
Manufacturer:
Atmel
Quantity:
10 000
22.7
22.7.1
8284A–AVR–10/10
ADC Noise Canceler
Analog Input Circuitry
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC
Noise Reduction and Idle mode. To make use of this feature, the following procedure should be
used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once
3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
The analog input circuitry for single ended channels is illustrated in
analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin,
regardless of whether that channel is selected as input for the ADC. When the channel is
selected, the source must drive the S/H capacitor through the series resistance (combined resis-
tance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
Signal components higher than the Nyquist frequency (f
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
must be selected and the ADC conversion complete interrupt must be enabled.
the CPU has been halted.
wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another
interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be
executed, and an ADC Conversion Complete interrupt request will be generated when
the ADC conversion completes. The CPU will remain in active mode until a new sleep
command is executed.
ADC
/2) should not be present for either
Figure 22-8 on page 227
226
An

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