ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 224

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.6
8284A–AVR–10/10
Changing Channel or Reference Selection
Figure 22-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 22-7. ADC Timing Diagram, Free Running Conversion
Table 22-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
ADC Conversion Time
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Conversion
Complete
3
One Conversion
Sample &
Hold
11
4
Sample & Hold (Cycles from
Start of Conversion)
12
5
6
13
7
One Conversion
Next Conversion
1
13.5
Sign and MSB of Result
LSB of Result
1.5
2
8
2
MUX and REFS
Update
9
3
10
Conversion
Complete
Sample & Hold
11
4
12
Conversion Time (Cycles)
13
Sign and MSB of Result
LSB of Result
13.5
25
13
Next Conversion
1
Prescaler
Reset
2
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