ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 272

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-5.
8284A–AVR–10/10
Step
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PR
ELOAD
EXTEST
Verify the
COMP bit
scanned out to
be 0
Verify the
COMP bit
scanned out to
be 1
Algorithm for Using the ADC
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
in the algorithm in
The column “Actions” describes what JTAG instruction to be used before filling the Boundary-
scan Register with the succeeding columns. The verification should be done on the data
scanned out when scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
ADCEN
(Sample mode).
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
1
1
1
1
1
1
1
1
1
1
1
The lower limit is:
The upper limit is:
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table
25-5. Only the DAC and port pin values of the Scan Chain are shown.
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1.5V 0.95 5V
1024 1.5V 1.05 5V
Table 25-4 on page 270
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⋅
⋅
⁄
⁄
PRECH
=
=
1
1
1
1
0
1
1
1
1
0
1
291
323
are used unless other values are given
=
=
0x123
0x143
PA3.
Data
CC
0
0
0
0
0
0
0
0
0
0
0
.
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0
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