ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 252

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5.4
8284A–AVR–10/10
LCDCCR – LCD Contrast Control Register
is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation
is shown in
Table 23-6.
• Bits 7:5 – LCDDC[2:0]: LDC Display Configuration
The LCDDC[2:0] bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static duty or blanking, drive
time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can
be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before chang-
ing LCDDC[2:0].
Table 23-7.
Note:
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% all the time, regardless of the drive time
configured by LCDDC[2:0].
Bit
(0xE7)
Read/Write
Initial Value
clk
4 MHz
4 MHz
32.768 kHz
32.768 kHz
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
LCD
LCDDC2
The drive time will be longer dependent on oscillator startup time.
0
0
0
0
1
1
1
1
Table 23-6 on page
LCDDC2
Example of frame rate calculation
LCD Display Configuration
R/W
duty
7
0
Static
1/4
1/3
1/2
LCDDC1
R/W
K
8
6
8
8
6
0
LCDDC1
0
0
1
1
0
0
1
1
252.
LCDDC0
2048
2048
R/W
16
16
5
0
N
LCDNDT
R
4
0
LCDCD2:0
011
011
000
100
LCDDC0
LCDCC3
0
1
0
1
0
1
0
1
R/W
3
0
D
4
4
1
5
LCDCC2
R/W
2
0
Nominal drive time
300 µs
70 µs
150 µs
450 µs
575 µs
850 µs
1150 µs
50% of clk
Frame Rate
4000000/(8*2048*4) = 61 Hz
4000000/(6*2048*4) = 81 Hz
32768/(8*16*1) = 256 Hz
32768/(8*16*5) = 51 Hz
LCDCC1
R/W
1
0
LCD_PS
LCDCC0
R/W
0
0
LCDCCR
252