ATMEGA649A-AU Atmel, ATMEGA649A-AU Datasheet - Page 251

• Manufacturer Part Number: ATMEGA649A-AU
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: ATmega
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8284A–AVR–10/10
Table 23-4.
• Bit 3 – Reserved
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD[2:0]: LCD Clock Divide 2, 1, and 0
The LCDCD[2:0] bits determine division ratio in the clock divider. The various selections are
shown in
selection.
Table 23-5.
The frame frequency can be calculated by the following equation:
Where:
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
LCDCD2
LCDPS2
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
1
1
1
0
0
0
0
1
1
1
1
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see
Table 23-5 on page
LCDCD1
LCDPS1
LCD Prescaler Select (Continued)
LCD Clock Divide
0
1
1
0
0
1
1
0
0
1
1
LCDCD0
LCDPS0
1
0
1
0
1
0
1
0
1
0
1
Table 23-5 on page
251. This Clock Divider gives extra flexibility in frame rate
divided by (D):
Output from
clk
clk
clk
f
Output from
Prescaler
frame
clk
Prescaler
LCD
LCD
LCD
LCD
/1024
/2048
/4096
1
2
3
4
5
6
7
8
=
/N
------------------------- -
(
K N D
251)
f
clk
⋅
LCD
Applied Prescaled LCD Clock Frequency
⋅
clk
when LCDCD2:0 = 0, Duty = 1/4, and
)
LCD
= 32.768 kHz, N = 16, and Duty =
1/4, gives a frame rate of:
Frame Rate = 64 Hz
520 kHz
1 MHz
2 MHz
85.3 Hz
51.2 Hz
42.7 Hz
36.6 Hz
256 Hz
128 Hz
64 Hz
32 Hz
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