AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 124

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.2.2
18.2.3
18.3
124
Memory Mapping
AT91SAM9260
Matrix Slaves
Master to Slave Access
Table 18-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 18-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following table.
Table 18-3.
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each
AHB Master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
performs remap action for every master independently.
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
2
3
4
0
1
External Bus Interface
UHP User Interface
Internal Peripherals
Internal SRAM
Internal SRAM
Internal ROM
Master
Slave
4 KBytes
4 KBytes
List of Bus Matrix Masters
List of Bus Matrix Slaves
AT91SAM9260 Masters to Slaves Access
Internal SRAM0 4 KBytes
Internal SRAM1 4 KBytes
Internal ROM
USB Host User Interface
External Bus Interface
Internal Peripherals
Instruction &
USB Host DMA
ISI Controller
Ethernet MAC
ARM926
0 & 1
Data
X
X
X
X
X
X
Peripheral
Controller
DMA
2
X
X
X
X
X
-
USB Host
Controller
X
X
X
X
X
3
-
Controller
ISI
X
X
X
4
-
-
-
6221I–ATARM–17-Jul-09
Ethernet
MAC
X
X
X
5
-
-
-