AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 602
![IC MCU ARM9 217LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9260B-CU-999
Manufacturer Part Number
AT91SAM9260B-CU-999
Description
IC MCU ARM9 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9260B-CU-999.pdf
(798 pages)
Specifications of AT91SAM9260B-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For con-
formance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations).
• RTY: Retry test
Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this
bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters
decrement time from 512 bit times, to every rx_clk cycle.
• PAE: Pause Enable
When set, transmission pauses when a valid pause frame is received.
• RBOF: Receive Buffer Offset
Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
• RLCE: Receive Length field Checking Enable
When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in
bytes 13 and 14 — length/type ID = 0600 — are not be counted as length errors.
• DRFCS: Discard Receive FCS
When set, the FCS field of received frames are not be copied to memory.
• EFRHD:
Enable Frames to be received in half-duplex mode while transmitting.
• IRXFCS: Ignore RX FCS
When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this
bit must be set to 0.
602
RBOF
CLK
00
01
10
11
00
01
10
11
AT91SAM9260
MDC
MCK divided by 8 (MCK up to 20 MHz)
MCK divided by 16 (MCK up to 40 MHz)
MCK divided by 32 (MCK up to 80 MHz)
MCK divided by 64 (MCK up to 160 MHz)
Offset
No offset from start of receive buffer
One-byte offset from start of receive buffer
Two-byte offset from start of receive buffer
Three-byte offset from start of receive buffer
6221I–ATARM–17-Jul-09
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