AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 762
AT91SAM9260B-CU-999
Manufacturer Part Number
AT91SAM9260B-CU-999
Description
IC MCU ARM9 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9260B-CU-999.pdf
(798 pages)
Specifications of AT91SAM9260B-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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43.2.8
43.2.8.1
43.2.8.2
43.2.9
43.2.9.1
43.2.9.2
43.2.9.3
762
AT91SAM9260
Oscillators
SDRAM Controller
On-chip RC Startup Time
Bad Sampling of OSCSEL
SDCLK Clock Active After Reset
Mobile SDRAM Device Initialization Constraint
JEDEC Standard Compatibility
When booting from the on-chip RC, the startup time is fixed at 1200 ms and not 240 µs as spec-
ified in
None
When VDDBU only is powered, either internal RC oscillator or external 32K osc may start
regardless of the setting of the OSCSEL pin. The OSCSEL pin sampling is correct after applying
VDDCORE power supply and remains correct if VDDCORE is removed.
The first power-up sequence requires both VDDBU and VDDCORE to correctly sample the
OSCSEL signal.
After a reset, the SDRAM clock is always active leading to over consumption in the pad.
The following sequence stops the SDRAM clock.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In the current revision, SDCKE rises at the same time as SDCK while exiting self-refresh mode.
To be fully compliant with the JEDEC standard, SDCK must be STABLE before the rising edge
of SDCKE.
None.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
END
Table 6-1 on page
15.
6221I–ATARM–17-Jul-09
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