AT91SAM9260B-CU-999 Atmel, AT91SAM9260B-CU-999 Datasheet - Page 758

• Manufacturer Part Number: AT91SAM9260B-CU-999
• Description: IC MCU ARM9 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.2.2
43.2.2.1
43.2.2.2
43.2.2.3
43.2.3
43.2.3.1
43.2.4
43.2.4.1
6221I–ATARM–17-Jul-09
Boot ROM
Bus Matrix
EMAC
NAND Flash Boot Does Not Work Correctly
Problem with RTT
User Reset trigger is enabled by default
Bus Matrix Master Configuration Register 5
TX Underrun May Occur in Some Cases
The SMC_SETUP register for the NAND Flash Chip Select (NCS3) is not initialized correctly in
the ROM code.
NRD_SETUP is initialized to “0” which leads to a violation of parameters tAR and tCLR.
The following commands are concerned; READ ID (0x90), READ STATUS (0x70), PAGE READ
(0x00, 0x30) and RANDOM DATA READ (0x05, 0xE0).
Use DataFlash Boot or external memory on EBI_NCS0.
The Real-time Timer is reset by the BootROM after each power up. This prevents using the RTT
as a backed up real-time clock.
Boot on an external memory connected on CS0 (BMS =0).
The boot ROM program configures the NRST pin as an input, and programs the User Reset
length. As RSTC registers are powered by VDDBU, the settings are saved and overwrite the
user configuration.
Writing the URSTEN bit to 0 in RSTC_MR disables the User Reset trigger.
MATRIX_MCFG5 is write-only. The value written is effective but not readable.
None.
EMACB FIFO internal arbitration scheme is:
EMACB master interface releases the AHB bus between two transfers.
EMACB has the highest priority.
If EMACB RX and TX FIFOs both have pending requests, the following sequence occurs:
1. Receive buffer manager write
2. Receive buffer manager read
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9260
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