P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 25

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
A typical I
direction bit (R/W), two types of data transfers are possible on the I
The P89V660/662/664 device provides two byte-oriented I
simplicity, the description in this text is written for the primary interface. However, unless
otherwise noted, the description applies to the secondary I
consideration given to the SFR’s addresses for the secondary interface. Please note that
the secondary I
pins. The interface has four operation modes: Master Transmitter mode, Master Receiver
mode, Slave Transmitter mode and Slave Receiver mode
The P89V660/662/664 CPU interfaces with the I
Registers (SFRs): S1CON (primary I
Data Register), S1STA (primary I
I
2
Fig 7.
•
•
•
•
•
•
•
C-bus Slave Address Register).
Multimaster bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a ‘not acknowledge’ is returned. The master device generates all of
the serial clock pulses and the START and STOP conditions. A transfer is ended with
a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I
released.
2
I
2
2
C-bus may be used for test and diagnostic purposes
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
2
C-bus interface uses quasi-bidirectional I/O pins instead of open-drain
P1[7]/SDA
Rev. 03 — 10 November 2008
P89V660/662/664
P1[6]/SCL
2
C-bus Status Register), and the S1ADR (primary
80C51 with 512 B/1 kB/2 kB RAM, dual I
2
C-bus Control Register), S1DAT (primary I
OTHER DEVICE
WITH I
R pu
Figure
INTERFACE
2
C-BUS
2
C-bus through four Special Function
7. Depending on the state of the
R pu
P89V660/662/664
2
2
OTHER DEVICE
C-bus interfaces. For
WITH I
C-bus interface with
INTERFACE
2
C-BUS
2
C-bus will not be
2
C-bus:
002aab911
© NXP B.V. 2008. All rights reserved.
SDA
SCL
2
C-bus, SPI
2
C-bus
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