P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 75

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
Fig 36. External program memory read cycle
PSEN
port 0
port 2
ALE
9.1 Explanation of symbols
Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time).
The other characters, depending on their positions, stand for the name of a signal or the
logical status of that signal. The following is a list of all the characters and what they stand
for.
A — Address
C — Clock
D — Input data
H — Logic level HIGH
I — Instruction (program memory contents)
L — Logic level LOW or ALE
P — PSEN
Q — Output data
R — RD signal
T — Time
V — Valid
W — WR signal
X — No longer a valid logic level
Z — High impedance (Float)
Example:
t
t
AVLL
LLPL
t
= Address valid to ALE LOW time
= ALE LOW to PSEN LOW time
AVLL
t
LHLL
t
LLAX
A0 to A7
Rev. 03 — 10 November 2008
t
LLPL
t AVIV
A8 to A15
t
PLAZ
80C51 with 512 B/1 kB/2 kB RAM, dual I
t
t
PLIV
LLIV
INSTR IN
t
PXIX
t
PXIZ
t
PLPH
P89V660/662/664
t
PXAV
A0 to A7
A8 to A15
002aaa548
© NXP B.V. 2008. All rights reserved.
2
C-bus, SPI
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