P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 31

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
STOP conditions are recognized as the beginning and end of a serial transfer. In a given
application, the I
I
these addresses is detected, an interrupt is requested. When the microcontrollers wishes
to become the bus master, the hardware waits until the bus is free before the master mode
is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the
master mode, the I
slave address in the same serial transfer.
2
Fig 12. Format of slave transmitter mode
C-bus hardware looks for its own slave address and the general call address. If one of
2
C-bus may operate as a master and as a slave. In the slave mode, the
2
C-bus switches to the slave mode immediately and can detect its own
from master to slave
from slave to master
S
Rev. 03 — 10 November 2008
slave address
logic 0 = write
logic 1 = read
80C51 with 512 B/1 kB/2 kB RAM, dual I
R
A
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
DATA
(n Bytes + acknowledge)
data transferred
A
P89V660/662/664
DATA
A
002aaa933
P
© NXP B.V. 2008. All rights reserved.
2
C-bus, SPI
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