P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 30

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
Fig 10. A Master Receiver switches to Master Transmitter after sending Repeated Start.
6.4.5.3 Slave receiver mode
6.4.5.4 Slave transmitter mode
from master to slave
from slave to master
S
In the Slave Receiver mode, data bytes are received from a master transmitter. To
initialize the Slave Receiver mode, the user should write the slave address to the Slave
Address Register (S1ADR) and the I
configured as follows:
Table 21.
CR2:0 are not used for slave mode. ENS1 must be set = 1 to enable I
bit must be set = 1 to acknowledge its own slave address or the general call address. STA,
STO and SI are cleared to 0.
After S1ADR and S1CON are initialized, the interface waits until it is addressed by its own
address or general address followed by the data direction bit which is 0(W). If the direction
bit is 1(R), it will enter Slave Transmitter mode. After the address and the direction bit have
been received, the SI bit is set and a valid status code can be read from the Status
Register(S1STA). Refer to
The first byte is received and handled as in the Slave Receiver mode. However, in this
mode, the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted via P1[7]/SDA while the serial clock is input through P1[6]/SCL. START and
Bit
Symbol
Value
SLA
Fig 11. Format of slave receiver mode
logic 0 = write
logic 1 = read
R
7
CR2
-
I
2
C-bus control register (S1CON - address D8H)
A
DATA
(n Bytes + acknowledge)
from master to slave
from slave to master
S
6
ENS1
1
Rev. 03 — 10 November 2008
data transferred
slave address
A
Table 25
DATA
5
STA
0
logic 0 = write
logic 1 = read
80C51 with 512 B/1 kB/2 kB RAM, dual I
A
for the status codes and actions.
W
2
C-bus Control Register (S1CON) should be
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
SLA = slave address
RS = repeat START condition
RS
4
STO
0
A
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
RS = repeated START condition
DATA
SLA
(n Bytes + acknowledge)
data transferred
3
SI
0
A
P89V660/662/664
W
DATA
A
2
AA
1
A/A
DATA
002aaa932
P/RS
2
A
1
CR1
-
C-bus function. AA
© NXP B.V. 2008. All rights reserved.
002aaa931
P
2
C-bus, SPI
0
CR0
-
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