P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 6

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
Table 3.
P89V660_662_664_3
Product data sheet
Symbol
P0[0] to P0[7]
P0[0]/AD0
P0[1]/AD1
P0[2]/AD2
P0[3]/AD3
P0[4]/AD4
P0[5]/AD5
P0[6]/AD6
P0[7]/AD7
P1[0] to P1[7]
P1[0]/T2
P1[1]/T2EX
P1[2]/ECI
P1[3]/CEX0
Pin description
Pin
TQFP44
37
36
35
34
33
32
31
30
40
41
42
43
5.2 Pin description
PLCC44
43
42
41
40
39
38
37
36
2
3
4
5
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O with
internal
pull-up
I/O
I
I/O
I
I/O
I
I/O
I/O
Rev. 03 — 10 November 2008
Description
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have ‘1’s written to them float, and in this state
can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses
to external code and data memory. In this application, it uses
strong internal pull-ups when making the transition to ‘1’s.
External pull-ups are required as a general purpose I/O port.
P0[0] — Port 0 bit 0.
AD0 — Address/data bit 0.
P0[1] — Port 0 bit 1.
AD1 — Address/data bit 1.
P0[2] — Port 0 bit 2.
AD2 — Address/data bit 2.
P0[3] — Port 0 bit 3.
AD3 — Address/data bit 3.
P0[4] — Port 0 bit 4.
AD4 — Address/data bit 4.
P0[5] — Port 0 bit 5.
AD5 — Address/data bit 5.
P0[6] — Port 0 bit 6.
AD6 — Address/data bit 6.
P0[7] — Port 0 bit 7.
AD7 — Address/data bit 7.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 1 pins are pulled high by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 1 pins that are externally
pulled LOW will source current (I
pull-ups. P1[5], P1[6], P1[7] have high current drive of 16 mA.
P1[0] — Port 1 bit 0.
T2 — External count input to Timer/Counter 2 or Clock-out
from Timer/Counter 2
P1[1] — Port 1 bit 1.
T2EX: Timer/Counter 2 capture/reload trigger and direction
control
P1[2] — Port 1 bit 2.
ECI — External clock input. This signal is the external clock
input for the PCA.
P1[3] — Port 1 bit 3.
CEX0 — Capture/compare external I/O for PCA Module 0.
Each capture/compare module connects to a Port 1 pin for
external I/O. When not used by the PCA, this pin can handle
standard I/O.
80C51 with 512 B/1 kB/2 kB RAM, dual I
P89V660/662/664
IL
) because of the internal
© NXP B.V. 2008. All rights reserved.
2
C-bus, SPI
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