MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 128
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Interrupt Module (S12SINTV1)
4.5
4.5.1
After system reset, software should:
4.5.2
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the
CPU.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, other I bit maskable interrupt requests can interrupt the
current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
4.5.3
4.5.3.1
Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine
whether an I bit maskable interrupts is qualified to wake-up the CPU or not, the same conditions as in
normal run mode are applied during stop or wait mode:
Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can
wake-up the MCU from stop mode.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is
shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details.
128
1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.
•
1. Service interrupt, that is clear interrupt flags, copy data, etc.
2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt
3. Process data
4. Return from interrupt by executing the instruction RTI
•
location (0xFF80–0xFFF9).
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
requests)
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU.
Initialization/Application Information
Initialization
Interrupt Nesting
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
1
.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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