MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 83

• Manufacturer Part Number: MC9S12P96CFT
• Description: MCU 16BIT 96K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P96CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
2.3.34
Freescale Semiconductor
Address 0x0252
Write: Anytime
DDRM
DDRM
DDRM
PTIM
Field
Field
Reset
5-0
5
4
3
W
R
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M Data Direction Register (DDRM)
0
0
7
0
0
6
Figure 2-32. Port M Data Direction Register (DDRM)
Table 2-30. DDRM Register Field Descriptions
Table 2-29. PTIM Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DDRM5
5
0
DDRM4
0
4
Description
Description
DDRM3
0
3
DDRM2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
DDRM1
0
1
DDRM0
0
0
83
(1)