MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 402
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 402 of 566
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Serial Peripheral Interface (S12SPIV5)
12.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
12.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3
This section provides a detailed description of address space and registers used by the SPI.
12.3.1
The memory map for the SPI is given in
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
402
Reserved
Reserved
Register
SPIDRH
SPICR1
SPICR2
SPIDRL
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
SPIBR
SPISR
Name
Memory Map and Register Definition
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
Bit 7
SPIE
SPIF
R15
T15
R7
T7
0
0
= Unimplemented or Reserved
SPPR2
XFRW
SPE
R14
T14
R6
T6
6
0
S12P-Family Reference Manual, Rev. 1.13
Figure 12-2. SPI Register Summary
Figure
SPPR1
SPTEF
SPTIE
R13
T13
R5
T5
5
0
12-2. The address listed for each register is the sum of a
MODFEN
SPPR0
MSTR
MODF
R12
T12
R4
T4
4
BIDIROE
CPOL
R11
T11
R3
T3
3
0
0
CPHA
SPR2
R10
T10
R2
T2
2
0
0
Freescale Semiconductor
SPISWAI
SSOE
SPR1
R9
R1
T9
T1
1
0
LSBFE
SPC0
SPR0
Bit 0
R8
R0
T8
T0
0
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