MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 351

• Manufacturer Part Number: MC9S12P96CFT
• Description: MCU 16BIT 96K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P96CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: anytime
Write: anytime
10.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases.
Read: anytime
Write: anytime
Freescale Semiconductor
Module Base + 0x001D
Module Base + 0x00E
PWMRSTRT
PWMLVL
PWMIE
PWMIF
Reset
Reset
Field
7
6
5
4
W
W
R
R
PWMIF
PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be
flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect.
0 No change on PWM5IN input.
1 Change on PWM5IN input
PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
0 PWM interrupt is disabled.
1 PWM interrupt is enabled.
PWM Restart — The PWM can only be restarted if the PWM channel input 5 is deasserted. After writing a logic 1
to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes
next “counter = 0” phase.
Also, if the PWM5ENA bit is reset to 0, the PWM do not start before the counter passes 0x0000.
The bit is always read as 0.
PWM Shutdown Output Level — If active level as defined by the PWM5IN input, gets asserted all enabled PWM
channels are immediately driven to the level defined by PWMLVL.
0 PWM outputs are forced to 0
1 PWM outputs are forced to 1.
Bit 7
1
0
7
7
= Unimplemented or Reserved
PWMIE
Figure 10-32. PWM Channel Duty Registers (PWMDTY5)
6
1
0
6
6
Figure 10-33. PWM Shutdown Register (PWMSDN)
Table 10-10. PWMSDN Field Descriptions
PWMRSTRT
S12P-Family Reference Manual, Rev. 1.13
5
1
0
0
5
5
PWMLVL
4
1
0
4
4
Description
Pulse-Width Modulator (PWM8B6CV1) Block Description
3
1
0
0
3
3
PWM5IN
2
1
0
2
2
PWM5INL
1
1
0
1
1
PWM5ENA
Bit 0
1
0
0
0
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