MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 167
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.3.2.7.3
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
the comparator enable bit in the associated DBGXCTL control register.
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2).
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
0
0
6
Table 6-20. State3 — Sequencer Next State Selection
Table 6-36
Figure 6-1
Either Match1 or Match2 to State1....... Match0 to Final State
Either Match1 or Match2 to Final State....... Match0 to State1
Table 6-19. DBGSCR3 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
and described in 6.3.2.8.1. Comparators must be enabled by setting
Match2 to State2........ Match0 to Final State
Match2 to State2........ Match1 to Final State
Match0 to State2....... Match2 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match1 to Final State
Match0 to Final State
0
0
4
Match0 to State1
Match1 to State2
Description
Reserved
Reserved
Reserved
Reserved
Reserved
SC3
0
3
SC2
0
2
S12S Debug Module (S12SDBGV2)
SC1
0
1
SC0
0
0
167
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