MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 217
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.3.2.9
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop Mode.
Read: Anytime
Write:
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP
time-out period.
In normal mode the COP time-out period is restarted if either of these conditions is true:
In special mode, any write access to CPMUCOP register restarts the COP time-out period.
Freescale Semiconductor
0x003C
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
Reset
1. RSBCK: anytime in special mode; write to “1” but not to “0” in normal mode
2. WCOP, CR2, CR1, CR0:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
2. Writing WCOP bit (anytime in special mode, once in normal mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
details.
W
R
— Anytime in special mode, when WRTMASK is 0, otherwise it has no effect
— Write once in normal mode, when WRTMASK is 0, otherwise it has no effect.
WRTMASK = 0.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
S12CPMU COP Control Register (CPMUCOP)
F
7
= Unimplemented or Reserved
RSBCK
Figure 7-12. S12CPMU COP Control Register (CPMUCOP)
0
6
WRTMASK
S12P-Family Reference Manual, Rev. 1.13
0
0
5
0
0
4
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
0
3
CR2
F
2
CR1
F
1
CR0
F
0
217
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