D13002X16V Renesas Electronics America, D13002X16V Datasheet - Page 10

• Manufacturer Part Number: D13002X16V
• Description: MCU 3/5V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7
7.1
7.2
7.3
7.4
7.5
Section 8
8.1
8.2
8.3
8.4
6.4.1
6.4.2
6.4.3
Overview ........................................................................................................................ 139
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions...................................................................................................... 142
7.2.1
7.2.2
7.2.3
7.2.4
Operation ........................................................................................................................ 148
7.3.1
7.3.2
7.3.3
7.3.4
Interrupt Source .............................................................................................................. 175
Usage Notes .................................................................................................................... 175
Overview ........................................................................................................................ 179
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Register Descriptions (1) (Short Address Mode) ........................................................... 184
8.2.1
8.2.2
8.2.3
8.2.4
Register Descriptions (2) (Full Address Mode).............................................................. 192
8.3.1
8.3.2
8.3.3
8.3.4
Operation ........................................................................................................................ 201
Connection to Dynamic RAM and Pseudo-Static RAM ................................ 135
Register Write Timing .................................................................................... 135
BREQ Input Timing........................................................................................ 137
Refresh Controller
Features........................................................................................................... 139
Block Diagram................................................................................................ 140
Input/Output Pins............................................................................................ 141
Register Configuration.................................................................................... 141
Refresh Control Register (RFSHCR) ............................................................. 142
Refresh Timer Control/Status Register (RTMCSR) ....................................... 145
Refresh Timer Counter (RTCNT)................................................................... 147
Refresh Time Constant Register (RTCOR) .................................................... 147
Area Division.................................................................................................. 148
DRAM Refresh Control.................................................................................. 149
Pseudo-Static RAM Refresh Control.............................................................. 164
Interval Timing ............................................................................................... 169
DMA Controller
Features........................................................................................................... 179
Block Diagram................................................................................................ 180
Functional Overview ...................................................................................... 181
Input/Output Pins............................................................................................ 182
Register Configuration.................................................................................... 182
Memory Address Registers (MAR)................................................................ 185
I/O Address Registers (IOAR)........................................................................ 186
Execute Transfer Count Registers (ETCR) .................................................... 186
Data Transfer Control Registers (DTCR) ....................................................... 188
Memory Address Registers (MAR)................................................................ 192
I/O Address Registers (IOAR)........................................................................ 192
Execute Transfer Count Registers (ETCR) .................................................... 193
Data Transfer Control Registers (DTCR) ....................................................... 195
........................................................................................ 179
.................................................................................... 139