D13002X16V Renesas Electronics America, D13002X16V Datasheet - Page 507

• Manufacturer Part Number: D13002X16V
• Description: MCU 3/5V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN
selected, after conversion of the first channel ends, conversion of the second channel (AN
AN
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN
described next. Figure 14-4 shows a timing diagram for this example.
1.
2.
3.
4.
5.
5
Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN
When A/D conversion of the first channel (AN
ADDRA. Next, conversion of the second channel (AN
Conversion proceeds in the same way through the third channel (AN
When conversion of all selected channels (AN
and conversion of the first channel (AN
interrupt is requested at this time.
Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN
) starts immediately. A/D conversion continues cyclically on the selected channels until the
0
to AN
2
are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
0
when CH2 = 0, AN
0
).
0
) starts again. If the ADIE bit is set to 1, an ADI
4
491
when CH2 = 1). When two or more channels are
0
0
) is completed, the result is transferred into
to AN
0
to AN
2
1
) is completed, the ADF flag is set to 1
) starts automatically.
2
) are selected in scan mode are
2
).
1
or