HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 158

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
6.2.5
BRCR is an 8-bit readable/writable register that enables address output on bus lines A
enables or disables release of the bus to an external device.
Bit
Initial value
Read/
Write
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA
0 in this bit enables A
modified and PA
Bit 7: A23E
0
1
Bit 6—Address 22 Enable (A22E): Enables PA
0 in this bit enables A
modified and PA
Bit 6: A22E
0
1
Rev. 3.00 Sep 27, 2006 page 130 of 872
REJ09B0325-0300
Modes 1, 2, 5, 7
Modes 3, 4, 6
Bus Release Control Register (BRCR)
4
5
has its ordinary input/output functions.
has its ordinary input/output functions.
A23E
Address 23 to 21 enable
These bits enable PA to
PA to be used for A
A
Description
PA
PA
Description
PA
PA
R/W
23
22
21
7
1
address output from PA
address output from PA
4
4
5
5
4
address output
is the A
is the PA
is the A
is the PA
A22E
R/W
23
22
6
1
4
5
address output pin
address output pin
/TP
/TP
4
5
/TIOCA
/TIOCB
A21E
R/W
23
6
5
1
to
1
1
4
5
input/output pin
input/output pin
. In modes other than 3, 4, and 6 this bit cannot be
. In modes other than 3, 4, and 6 this bit cannot be
4
5
to be used as the A
to be used as the A
Reserved bits
4
1
3
1
23
22
address output pin. Writing
address output pin. Writing
2
1
Bus release enable
Enables or disables
release of the bus to
an external device
1
1
(Initial value)
(Initial value)
23
to A
BRLE
R/W
R/W
21
0
0
and